As semiconductor technology develops, the number of transistors included in a single integrated circuit, or “chip” is becoming larger and the design rule parameters therefore are becoming smaller. These two developments contribute to increased metal layer resistance and to difficulties associated with this increased resistance. Such difficulties include ground bounce, cross talk noise, and circuit delays. All of these difficulties slow down chip operation and may even corrupt data stored on the chip. Eliminating the impact of increased metal layer resistance is an important design challenge in most semiconductor designs, including designs for dynamic random access memory (DRAM) devices.
One solution to this problem has been the development of a meshed power bus system for the chip, as described in Yamada, A 64-Mb DRAM with Meshed Power Line, 26 IEEE Journal of Solid-State Circuits 11 (1991). A meshed power bus system is readily implemented in integrated circuits like DRAMs because of their large arrays of memory cells and the presence of distributed sense amplifier drivers. The meshed system supplies adequate power to the distributed sense amplifier drivers because the system has many power buses running in both horizontal and vertical directions across the arrays.
The Yamada meshed system may be implemented using a conventional complimentary metal oxide semiconductor (CMOS) technology, including first, second and third metal layers, each electrically isolated from each other, wherein the first metal layer represents the lowest metal layer, the third metal layer represents the upper-most metal layer, and the second metal layer lies between the first and third layers. The Yamada meshed system is constructed in the second and third metal layer and includes a positive supply voltage (VDD) mesh and a negative supply voltage (VSS) mesh, for the VDD power buses and the VSS power buses, respectively. Conventional designs have these meshes running over the memory array and connecting at the sense amplifiers. Connections are made using through-holes, located in the area of the sense amplifier circuits. However, the presence of VDD and VSS power buses in the sense amplifiers is unnecessary, since these circuits do not require either VDD or VSS power buses, except for well bias.
As a result, the sense amplifiers, due to their relatively small size and numerous associated signal and power buses, are adversely affected by the Yamada meshed system. The Yamada meshed system overcrowds the sense amplifiers with additional power and signal buses. In addition, the metal line width required for overlapping through-holes is larger than the minimum metal line width and therefore increases the width of the metal layers even further. As a result, the metal layer over the sense amplifiers becomes determinative of the size of the sense amplifier circuits. Accordingly, their size reduction must be realized by tightening the metal width, inevitably resulting in increased resistance and slower operation.
In addition to the Yamada meshed system, other proposals have been made for conventional DRAM design. Recently, a hierarchical word line scheme was proposed in K. Noda et Al., a Boosted Dual Word-line Decoding Scheme for 256 Mbit DRAM's, 1992 Symp. on VLSI Circuits Dig. of Tech. Papers, pp. 112–113 (1992). The Noda scheme includes main word lines, constructed in the second metal line layer, and subword lines constructed in a poly silicon layer. The Noda scheme describes two main word lines (one true, one bar) for every eight subword lines, and is thereby able to relax the main word line pitch to four times that of the subword line. However, this pitch would not support an improved meshed power and signal bus system.
Consequently, there is a need for a meshed power and signal bus system on an array-type integrated circuit that does not limit mesh through-hole connections to the area of the sense amplifiers, but provides for such connections at other locations on the array, thereby allowing for a relaxed metal width over the sense amplifiers and a reduction of the overall area of the chip with lower power bus resistance.
Furthermore, there is a need for a hierarchical word line scheme that supports an improved meshed power and signal bus system, that has a main word line pitch greater than four times that of the subword line pitch.